1. Field of the Invention
This invention relates to the field of semiconductor fabrication technology, and more specifically, to a method of adhering a passivation layer to a gold metalization region in a semiconductor device.
2. Description of the Prior Art
It is basic to the fabrication of semiconductor devices that a passivation layer be deposited over the surface of the completed device so as to protect it from contaminants, moisture or particles which could affect the operation of the device. In addition, the passivation layer is used to control the surface states of the semiconductor to insure uniform behavior of the device. The passivation layer is usually an oxide of the semiconductor, such as SiO.sub.2 and Al.sub.2 O.sub.3. However, other materials such as Si.sub.3 N.sub.4 are also used.
It is also well recognized in the field of integrated circuit semiconductor fabrication technology that gold has many desirable electrical properties which make it suitable for use as a metallization region. For example, gold has low resistivity which facilitates the transmission of high current densities through a thin layer of gold. However, gold does not adhere well to silicon dioxide or other passivation materials, which makes it difficult to be employed directly as the first level of metal contacts in semiconductor devices, and particularly in metalization regions. Even so, gold has been used to form integrated circuit devices. In LSI (large scale integrated circuits), multi-layer metalization is required in the integrated circuit structure. In order for the multi-layer metalization to be effective when gold is used, there must be a layer of passivation, such as glass, between the gold layers. This has led to a number of problems including the separation of two or more layers of gold. This is believed to be due to lack of satisfactory adherence of the passivation layer to be gold. Failure of the passivation layer to adhere satisfactorily to the gold causes the passivation layer to peel or flake off thereby resulting in device failure. This problem becomes especially severe when large areas of gold are to be passivated. As a result of this nonadherence, the passivation layer on the gold metalization region is also vulnerable to cracks or fractures in its surface, which can also result in device failure.
Yet another problem relates to the bonding of contact leads to the gold metalization on the semiconductor wafer. Typically, the passivation layer is applied over the entire surface of the semiconductor including the gold metalization regions. Then, in order to electrically connect leads to the gold metalization contacts, a sufficient amount of the passivation layer over the gold metalization regions is removed to allow a bond to be made. This method of making contact to the gold metalization regions is used primarily in large scale integration (LSI) technology where multiple layers of gold may be deposited on one semiconductor wafer. The removal of the passivation layer overlying the gold metalization region is usually accomplished by means of a wet etching and masking process which selectively removes the passivation material in certain desired regions. A problem with this is that when a passivation layer is used which does not adhere well to the gold, the wet etching step will, in addition to removing the passivation layer, also tend to remove some of the passivation material which is situated long the gold-passivation material interface. This results in the "undermining" of the passivation material. Such undermining can lead to the separation of the passivation layer from the underlying gold layer, resulting in unreliability or failure of the device.
The art, in recognition of the benefits of using gold, but aware of the problem with its poor adherence to passivation layers, has devised a number of bonding techniques. One prior art method of adhering gold to an insulating layer is set forth in U.S. Pat. No. 3,832,230. In the method disclosed, metal film such as tantalum, zirconium, niobium or hafnium is deposited on the gold metalization contact region. The metal film is then heated in an oxidizing atmosphere to form an oxide. A layer of glass is deposited over the metal oxide layer. The glass adheres to the oxide which in turn adheres to the gold. This method is somewhat effective in preventing the cracking or separation of the passivation layer from the underlying gold regions. However, it necessitates heating the device in an oxidizing atmosphere to temperatures which can damage certain types of power transistors. For example, the reaction between tantalum and an oxidizing atmosphere will only take place at high temperatures. Without this oxidation treatment of the tantalum (or of the other metals mentioned above), the presence of the metal between the gold metalization contacts on the surface of the semiconductor will cause shorting of the contacts together, thereby causing the device to fail. Thus, in addition to heating, any residual unoxidized metal must be removed by a photo masking technique, which can substantially increase the price of manufacture. Yet another difficulty which results when this process is utilized is that the reactive metal normally tends to diffuse into the gold. This diffusion of metal into the gold tends to reduce the conductivity of the gold and thereby negates one of the purposes for using gold in the first place.
Another patent, U.S. Pat. No. 3,717,563, discloses a method for alleviating the gold-passivation problem by utilizing a beta tantalum instead of body centered cubic tantalum. When beta tantalum is used to form a sandwich with the gold contact layer, improvements are allegedly obtained. However, this method does not relieve the need to heat the device, and requires that multiple layers be formed.
It is therefore an objective of the present invention to provide a method for adhering gold to a passivation layer without requiring the heating of the entire device. The method of present invention achieves this and other objectives and therefore represents an advancement in the art of semiconductor manufacturing techniques.